SPSA068 datasheet(22/49 Pages) STMICROELECTRONICS

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SPI format and register mapping

A 32-bit SPI bus is used for bidirectional communication with the microcontroller and for functional and test

purpose.

A write operation leads to a modification of the addressed data by the payload if a write access is allowed (for

example control register, valid data). A read operation (based on previous communication request) shifts out the

data present in the addressed register (out of frame data exchange protocol).

A read and clear operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by

payload bits set to 0.

Table 6. SPI DI and SPI DO frames

Bit

30 29 28 27 26 25 24 23

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS

NVM

CODE

DATA WRITE

CRC

SPI

ERR

IERR

ADDRESS FDBACK

DATA READ

CRC

Logic content is reset only by POR activation, once VBAT1 falls below the POR threshold. WD_TWIN is not reset

by a reset command (or a WD fail) regardless of ‘WD_REC_en’ value.

DI stream:

•

Bit 31: R/W flag. To select read (0) or write (1) operation

•

Bit 30-23: SPI register address

•

Bit 22-21: NVM CODE:

–

00 NVM NOP (NVM code/address error: in case the address field is relative to NVM

operation,SPI_ERR is set)

–

01 NVM SOFT TRIM (NVM code/address error: in case the address field is not relative to NVM

operation,SPI_ERR is set)

–

10 NVM WRITE (NVM code/address error: in case the address field is not relative to NVM

operation,SPI_ERR is set)

–

11 NVM NOP (NVM code/address error: in case the address field is relative to NVM

operation,SPI_ERR is set)

•

Bit 20-5: Data to be written at a selected address

•

Bit 4-0: CRC code

DO stream:

•

Bit 31: Previous SPI communication error (frame length error, CRC error, MOSI stuck error, address error,

NVM code/address error)

•

Bit 30:NRST

•

Bit 29: FAULT

•

Bit 28:21: SPI register address (related to the previous transmission)

•

Bit 20-5: Data read at selected address (related to previous transmission)

•

Bit 4-0: CRC code

Note:

Bit 29 and bit 30 reflect the current status of NRST pin and FAULT pin. Every time the relevant SPI register is

accessed, an internal register will sample the current status of RSTB and FAULT pins, store them, then shift

them out on SPI DO frame at the next SPI access.

SPSA068

SPI format and register mapping

DS14755 - Rev 1

page 22/49

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