DAC8564 datasheet(5/51 Pages) TI2

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DAC8565

OUT

H/V

OUT

REF

LDAC

ENABLE

RSTSEL

RST

REF

GND

OUTC

OUTD

IOV

10 SCLK

SYNC

DAC8565

www.ti.com

SBAS411C

– JUNE 2007 – REVISED MARCH 2011

PIN CONFIGURATIONS

PW PACKAGE

TSSOP-16

(Top View)

PIN DESCRIPTIONS

NAME

DESCRIPTION

VOUTA

Analog output voltage from DAC A

VOUTB

Analog output voltage from DAC B

VREFH/

Positive reference input / reference output 2.5V if internal reference used.

VREFOUT

AVDD

Power-supply input, 2.7V to 5.5V

VREFL

Negative reference input

GND

Ground reference point for all circuitry on the part

VOUTC

Analog output voltage from DAC C

VOUTD

Analog output voltage from DAC D

Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output

SYNC

updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as

an interrupt, and the write sequence is ignored by the DAC8565. Schmitt-Trigger logic Input.

SCLK

Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic Input.

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.

DIN

Schmitt-Trigger logic Input.

IOVDD

Digital input-output power supply

Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or to

RST

midscale (RSTSEL = 1).

RSTSEL

Reset select. If RSTSEL is low, input coding is binary; if high = two

's complement.

ENABLE

The enable pin (active low) connects the SPI interface to the serial port

LDAC

Load DACs; rising edge triggered, loads all DAC registers

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