STM32L4S5AI datasheet(22/275 Pages) STMICROELECTRONICS

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Functional overview

STM32L4S5xx, STM32L4S7xx and STM32L4S9xx

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DocID030322 Rev 2

3.10

Power supply management

3.10.1

Power supply schemes

The STM32L4x devices require a 1.71 V to 3.6 V VDD operating voltage supply. Several

independent supplies can be provided for specific peripherals:

•

VDD = 1.71 V to 3.6 V

VDD is the external power supply for the I/Os, the internal regulator and the system

analog such as reset, power management and internal clocks. It is provided externally

through the VDD pins.

•

VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) to 2.4 V (VREFBUF) to 3.6 V

VDDA is the external analog power supply for A/D converters, D/A converters, voltage

reference buffer, operational amplifiers and comparators. The VDDA voltage level is

independent from the VDD voltage and should preferably be connected to VDD when

these peripherals are not used.

•

VDDUSB = 3.0 V to 3.6 V

VDDUSB is the external independent power supply for USB transceivers. The

VDDUSB voltage level is independent from the VDD voltage and should preferably be

connected to VDD when the USB is not used.

•

VDDIO2 = 1.08 V to 3.6 V

•

VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage

level is independent from the VDD voltage and should preferably be connected to VDD

when PG[15:2] are not used.

•

VDDDSI is an independent DSI power supply dedicated for DSI regulator and MIPI D-

PHY. This supply must be connected to the global VDD.

•

VCAPDSI pin is the output of DSI regulator (1.2 V) which must be connected externally

to VDD12DSI.

•

VDD12DSI pin is used to supply the MIPI D-PHY, and to supply clock and data lanes

pins. An external capacitor of 2.2 uF must be connected on the VDD12DSI pin.

•

VBAT = 1.55 V to 3.6 V

VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers

(through power switch) when VDD is not present.

•

VREF-, VREF+

VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the

internal voltage reference buffer when enabled.

When VDDA < 2 V VREF+ must be equal to VDDA.

When VDDA ≥ 2 V VREF+ must be between 2 V and VDDA.

VREF+ can be grounded when ADC and DAC are not active.

The internal voltage reference buffer supports two output voltages, which are

configured with VRS bit in the VREFBUF_CSR register:

–VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.

–VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.

VREF- and VREF+ pins are not available on all packages. When not available, they are

bonded to VSSA and VDDA, respectively.

When the VREF+ is double-bonded with VDDA in a package, the internal voltage

reference buffer is not available and must be kept disable (refer to datasheet for

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