SN74ACT08EP

QUADRUPLE 2INPUT POSITIVEAND GATE

SCAS779 − SEPTEMBER 2004

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree†

D 4.5-V to 5.5-V VCC Operation

† Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D Inputs Accept Voltages to 5.5 V

D Max tpd of 10 ns at 5 V

D Inputs Are TTL-Voltage Compatible

description/ordering information

The SN74ACT08 is a quadruple 2-input positive-AND gate. This device performs the Boolean functions

Y = A

 B or Y = A + B in positive logic.

ORDERING INFORMATION

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 85°C

SOIC − D

Tape and reel

SN74ACT08IDREP

SACT08IEP

‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A

B

OUTPUT

Y

H

H

H

L

XL

X

L

L

logic diagram, each gate (positive logic)

Y

A

B

Copyright

 2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

VCC

4B

4A

4Y

3B

3A

3Y