WM8994ECSSLASHR datasheet(95/363 Pages) CIRRUS

95 / 363 page

WM8994

Rev 4.6

AIF1 - OUTPUT PATH HIGH PASS FILTER

A digital high-pass filter can be enabled in the AIF1 output paths to remove DC offsets. This filter is

enabled independently in the four AIF1 output channels using the register bits described in Table 36.

The HPF cut-off frequency for the AIF1 Timeslot 0 channels is set using AIF1ADC1_HPF_CUT. The

HPF cut-off frequency for the AIF1 Timeslot 1 channels is set using AIF1ADC2_HPF_CUT.

In hi-fi mode, the high pass filter is optimised for removing DC offsets without degrading the bass

response and has a cut-off frequency of 3.7Hz when the sample rate (fs) = 44.1kHz.

In voice modes, the high pass filter is optimised for voice communication; it is recommended to set the

cut-off frequency below 300Hz.

Note that the cut-off frequencies scale with the AIF1 sample rate. (The AIF1 sample rate is set using

the AIF1_SR register

, as described in the “Clocking and Sample Rates” section.) See Table 37 for the

HPF cut-off frequencies at all supported sample rates.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1040 (0410h)

AIF1 ADC1

Filters

14:13

AIF1ADC1_

HPF_CUT

[1:0]

AIF1ADC1 output path (AIF1, Timeslot 0)

Digital HPF cut-off frequency (fc)

00 = Hi-fi mode (fc = 4Hz at fs = 48kHz)

01 = Voice mode 1 (fc = 64Hz at fs = 8kHz)

10 = Voice mode 2 (fc = 130Hz at fs = 8kHz)

11 = Voice mode 3 (fc = 267Hz at fs = 8kHz)

AIF1ADC1L_

HPF

AIF1ADC1 (Left) output path (AIF1, Timeslot

0) Digital HPF Enable

0 = Disabled

1 = Enabled

AIF1ADC1R

_HPF

AIF1ADC1 (Right) output path (AIF1, Timeslot

0) Digital HPF Enable

0 = Disabled

1 = Enabled

R1041 (0411h)

AIF1 ADC2

Filters

14:13

AIF1ADC2_

HPF_CUT

[1:0]

AIF1ADC2 output path (AIF1, Timeslot 1)

Digital HPF cut-off frequency (fc)

00 = Hi-fi mode (fc = 4Hz at fs = 48kHz)

01 = Voice mode 1 (fc = 64Hz at fs = 8kHz)

10 = Voice mode 2 (fc = 130Hz at fs = 8kHz)

11 = Voice mode 3 (fc = 267Hz at fs = 8kHz)

AIF1ADC2L_

HPF

AIF1ADC2 (Left) output path (AIF1, Timeslot

1) Digital HPF Enable

0 = Disabled

1 = Enabled

AIF1ADC2R

_HPF

AIF1ADC2 (Right) output path (AIF1, Timeslot

1) Digital HPF Enable

0 = Disabled

1 = Enabled

Table 36 AIF1 Output Path High Pass Filter

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