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ADL6337ACRZD-R7 Datasheet(PDF) 5 Page - Analog Devices

Part # ADL6337ACRZD-R7
Description  35 dB Gain, 500 MHz to 5200 MHz Transmit VGA
PDF  53 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADL6337ACRZD-R7 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
ADL6337
SPECIFICATIONS
analog.com
Rev. E | 5 of 53
Table 2. Electrical Characteristics (Continued)
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Noise Figure
DSA = 0 dB
4.5
dB
DSA = 16 dB
9.0
dB
RF INPUT/OUTPUT CHARACTERISTICS
Input
Impedance
Differential
50
Ω
Return Loss
Inband, see the RF Input and Output section
10
15
dB
Output
Impedance
Single-ended
50
Ω
Return Loss
Inband
10
18
dB
Gain Flatness, fc > 1.5 GHz
Over ±100 MHz bandwidth
±0.1
dB
Over ±250 MHz bandwidth
±0.2
dB
Over ±500 MHz bandwidth
±0.9
dB
Gain Flatness, 0.5 GHz < fC < 1.5 GHz
Over ±40 MHz bandwidth
±0.1
dB
Over ±100 MHz bandwidth
±0.2
dB
Over ±200 MHz bandwidth
±0.5
dB
Settling Time for Disable to Enable
1
μs
Settling Time for Enable to Disable
1
μs
DSA Attenuation
Range
31.5
dB
Step Size
0.4
0.5
0.6
dB
Gain Settling Time
Minimum attenuation to maximum attenuation
387
ns
Maximum attenuation to minimum attenuation
1700
ns
POWER SUPPLY
Voltage
4.75
5.0
5.25
V
Supply Current
High performance mode
460
mA
Low power mode
380
400
mA
Power-Down Current
14
mA
DIGITAL LOGIC
Input Voltage
SCLK, SDIO, CS, CS_A2, CS_A1, CS_A0, TXENP
High (VIH)
1.07
V
Low (VIL)
0.68
V
Input Current
High (IIH)
−100
μA
Low (IIL)
100
μA
Output Voltage
SDO
At 1.8 V
Register 0x121, Bit 4 = 0x0
High (VOH)
Output high current (IOH) = −100 μA or −1 mA static load
1.5
V
Low (VOL)
Output low current (IOL) = 100 μA or 1 mA static load
0.2
V
At 3.3 V
Register 0x121, Bit 4 = 0x1
High (VOH)
IOH = −100 μA or −1 mA static load
2.7
V
Low (VOL)
IOL = 100 μA or 1 mA static load
0.2
V
DIGITAL LOGIC TIMING
Table 3. SPI AC Timing
Parameter
Description
Min
Typ
Max
Unit
fSCLK
Maximum serial clock rate, 1/tSCLK
25
MHz
tPWH
Minimum period that SCLK is in logic-high state
10
ns
tPWL
Minimum period that SCLK is in logic-low state
10
ns



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