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DFPMU-DP Datasheet(PDF) 2 Page - Digital Core Design |
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DFPMU-DP Datasheet(HTML) 2 Page - Digital Core Design |
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2 / 6 page ![]() All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. ● ● ● ● ● ● ● ● ● ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ○ ● ● ○ ○ ○ ○ ○ ○ ● ● ♦ ◊ ◊ ◊ ◊ ♦ ◊ ◊ ◊ ◊ ♦ ◊ ◊ ◊ ♦ ♦ ♦ ◊ ◊ http://www.DigitalCoreDesign.com http://www.dcd.pl FSIN, FCOS – sine, cosine KEY FEATURES Direct replacement for C double, float software functions such as: +, -, *, /,==, !=,>=, <=, <, > Configurability of all available functions C interface supplied for all popular compil- ers: GNU C/C++, 8051 compilers No programming required IEEE-754 Double precision real format support – double type IEEE-754 Single precision real format support – float type 8-bit, 16-bit 32-bit and 52-bit integers for- mat supported – integer types Flexible arguments and result registers location Performs the following functions: FADD, FSUB – addition, subtraction FMUL, FDIV – multiplication, division FSQRT – square root FXAM – examine input data FUCOM – comparison FTAN – tangent FATAN – arctangent FCLD, FILD – 8-bit, 16-bit integer to dou- ble FLLD, FELD – 32-bit, 52-bit integer to double FCST, FIST – double to 8-bit, 16-bi inte- ger FLST, FEST – double to 32-bit, 52-bit in- teger FFLD – float to double FFST – double to float Exceptions built-in routines Masks each exception indicator: Precision lack PE Underflow result UE Overflow result OE Invalid operand IE Division by zero ZE Denormal operand DE Fully configurable Fully synthesizable, static synchronous design with no internal tri-states DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted Netlist or/and plain text EDIF netlist VHDL & VERILOG test bench environ- ment Active-HDL automatic simulation mac- ros NCSim automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance ● Delivery the IP Core updates, minor and major versions changes ● Delivery the documentation updates ● Phone & email support |
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