LTC1867IGN datasheet(12/16 Pages) LINER

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LTC1863/LTC1867

18637f

Digital Interface

The LTC1863/LTC1867 have very simple digital interface

that is enabled by the control input, CS/CONV. A logic

rising edge applied to the CS/CONV input will initiate a

conversion. After the conversion, taking CS/CONV low will

enable the serial port and the ADC will present digital data

in two’s complement format in bipolar mode or straight

binary format in unipolar mode, through the SCK/SDO

serial port.

Internal Clock

The internal clock is factory trimmed to achieve a typical

conversion time of 3

µs and a maximum conversion time,

3.5

µs, over the full operating temperature range. The

typical acquisition time is 1.1

µs, and a throughput sam-

pling rate of 200ksps is tested and guaranteed.

Automatic Nap Mode

The LTC1863/LTC1867 go into automatic nap mode when

CS/CONV is held high after the conversion is complete.

With a typical operating current of 1.3mA and automatic

150

µA nap mode between conversions, the power dissi-

pation drops with reduced sample rate. The ADC only

keeps the VREF and REFCOMP voltages active when the

part is in the automatic nap mode. The slower the sample

rate allows the power dissipation to be lower (see

Figure 5).

REFERENCE

AMP

µF

2.2

µF

REFCOMP

GND

VREF

2.5V

4.096V

LTC1863/LTC1867

1867 F04a

BANDGAP

REFERENCE

0.1

µF

1867 F04b

LT1019A-2.5

VOUT

VIN

VREF

LTC1863/

LTC1867

GND

REFCOMP

2.2

µF

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the

second through Nth harmonics.

Internal Reference

The LTC1863/LTC1867 has an on-chip, temperature com-

pensated, curvature corrected, bandgap reference that is

factory trimmed to 2.5V. It is internally connected to a

reference amplifier and is available at VREF (Pin 10). A 6k

resistor is in series with the output so that it can be easily

overdriven by an external reference if better drift and/or

accuracy are required as shown in Figure 4. The reference

amplifier gains the VREF voltage by 1.638V to 4.096V at

REFCOMP (Pin 9). This reference amplifier compensation

pin, REFCOMP, must be bypassed with a 10

µF ceramic or

tantalum in parallel with a 0.1

µF ceramic for best noise

performance.

Figure 4b. Using the LT1019-2.5 as an External Reference

Figure 4a. LT1867 Reference Circuit

APPLICATIO S I FOR ATIO

fSAMPLE (ksps)

2.0

1.5

1.0

0.5

100

1000

18637 G10

VDD = 5V

Figure 5. Supply Current vs fSAMPLE

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