AS7C256B datasheet(1/8 Pages) ALSC

Part #	AS7C256B

Description	5V 32K X 8 CMOS SRAM (Common I/O)

PDF	8 Pages

Scroll/Zoom	100%

Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

Logo

1 / 8 page

September 2006

Advance Information

AS7C256B

12/5/06; V.1.0

Alliance Memory

P. 1 of 8

5V 32K X 8 CMOS SRAM (Common I/O)

®

Features

• Industrial (-40o to 85oC) temperature

• Organization: 32,768 words × 8 bits

• High speed

- 12 ns address access time

- 6 ns output enable access time

• Low power consumption via chip deselect

• One chip select plus one Output Enable pin

• Bidirectional data inputs and outputs

• TTL-compatible

• 28-pin JEDEC standard packages

- 300 mil SOJ

-8

× 13.4 mm TSOP

- 300 mil PDIP

• ESD protection

≥ 2000 volts

Logic block diagram

A

9

A

8

32,768 X 8

Array

(262,144)

Input buffer

A0

A1

A2

A3

A4

A5

A6

A7

A

10

A

11

A

12

A

13

A

14

I/O0

I/O7

VCC

GND

OE

CE

WE

Address decoder

Control

circuit

Pin arrangement

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

VCC

WE

A13

A8

A9

A11

OE

A10

CE

I/O7

I/O6

I/O5

I/O4

I/O3

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

GND

AS7C256B

16

15

28-pin TSOP 1 (8×13.4mm)

28-pin DIP, SOJ (300 mil)

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

(21)

(20)

(19)

(18)

(17)

(16)

(15)

(14)

(13)

(12)

(11)

(10)

(9)

(8)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

VCC

WE

A13

A8

A9

A11

OE

A10

CE

I/O7

I/O6

I/O5

I/O4

I/O3

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

GND

16

15

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AS7C256B Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation

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