STM32MP251D datasheet(40/241 Pages) STMICROELECTRONICS

40 / 241 page

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Bus error management

–

M0, M1, M2, and M3, when controller

–

S0, S1, S2, S3, S4, S5, and S6 when target

–

bus control switch error and recovery

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target reset

•

Separately programmed event/flag generation and management

–

Separated identification and clear control

–

Host application notification via event/flag polling, and/or via interrupt with a perevent programmable

enable

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Error type identification

•

Autonomous mode and transfers during Sleep and Stop modes via DMA

•

Autonomous wake

‑up on

–

Slave request acknowledge, when controller

–

Missed start detection, when target

–

Reset pattern detection, when target

3.51

Universal synchronous asynchronous receiver transmitter (USART1/2/3/6,

UART4/5/7/8/9)

STM32MP25xA/D devices embed four USART and five UART (see Table 8. USART/UART features for feature

summary).

These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor

communication mode, single-wire half-duplex communication mode, and have LIN master/slave capability. They

provide hardware management of CTS and RTS signals, and RS485 Driver Enable. They can communicate at

speeds of up to 10 Mbit/s.

The USARTs embed a 64-bytes transmit FIFO (TXFIFO) and a 64-bytes receive FIFO (RXFIFO). The FIFO mode

is enabled by software, and is disabled by default.

All USARTs provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. They have a

clock domain independent from the CPU clock: this allows the USARTx to wake up the device from Stop mode

using baudrates up to 200 Kbaud. Wake-up events from Stop mode are programmable and can be one of the

following:

•

start bit detection

•

any received data frame

•

a specific programmed data frame

All USARTs can be served by the DMA controller.

STM32MP251A/D STM32MP253A/D STM32MP255A/D STM32MP257A/D

Functional overview

DS14285 - Rev 3

page 40/241

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