P4C149-25LSMB datasheet(4/10 Pages) PYRAMID

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P4C148/P4C149

Page 4 of 10

Document # SRAM104 REV B

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE

WE CONTROLLED)(9)

Notes:

9. CE and WE must be LOW for WRITE cycle.

10. If CE goes HIGH simultaneously with WE high, the output remains in a high impedance state.

11. Write Cycle Time is measured from the last valid address to the first transition address.

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE

CE/CS

CS CONTROLLED)(9)

AC CHARACTERISTICS—WRITE CYCLE

CC = 5V ± 10%, All Temperature Ranges)

(2)

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max

tWC Write Cycle Time

tCW Chip Enable Time to End of Write

tAW Address Valid to End of Write

tAS

Address Set-up Time

00000

000

tWP Write Pulse Width

tAH Address Hold Time from End of Write

00000

000

tDW Data Valid to End of Write

5679

tDH Data Hold Time

00000

000

tWZ Write Enable to Output in High Z

56778

tOW Output Active from End of Write

00000

000

Sym

Parameter

-10

-12

-45

-55

-15

-20

-25

-35

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