OCT 17-06 RevB

SP705 Low Power Microprocessor Supervisory Circuits

© 2006 Sipex Corporation

10

Typically, WDO will be connected to the

non-maskable interrupt input (NMI) of a

µP.

When V

WDO will go LOW whether or not the watch-

dog timer has timed out. Normally this would

trigger an NMI but RESET goes LOW simulta-

neously, and thus overrides the NMI.

If WDI is left unconnected, WDO can be used as

a low-line output. Since floating WDI disables

the internal timer, WDO goes LOW only when

V

tioning as a low-line output.

Figure 14. SP705/706/813L/813M Watchdog Timing Waveforms

Figure 15. SP705/706 Timing Diagrams with WDI Tri-stated. The SP707/708/813L/813M RESET Output is the Inverse

of the RESET Waveform Shown.

RESET*

WDO

0V

+5V

WDI

RESET*

0V

+5V

0V

+5V

0V

+5V

* externally triggered LOW by MR,

RESET is for the SP813L/813M only

RESET

0V

+5V

0V

+5V

0V

+5V

0V

+5V

MR*

WDO

*externally driven LOW