AD8251ARMZ-R7 datasheet(17/24 Pages) AD

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AD8251

Rev. 0 | Page 17 of 24

Table 5. Truth Table Logic Levels for Transparent Gain Mode

Gain

−VS

Low

−VS

Low

High

−VS

High

Low

−VS

High

Latched Gain Mode

Some applications have multiple programmable devices such as

multiplexers or other programmable gain instrumentation

amplifiers on the same PCB. In such cases, devices can share a

data bus. The gain of the AD8251 can be set using WR as a latch,

allowing other devices to share A0 and A1. Figure 51 shows a

schematic using this method, known as latched gain mode. The

AD8251 is in this mode when WR is held at logic high or logic

low, typically 5 V and 0 V, respectively. The voltages on A0 and

A1 are read on the downward edge of the WR signal as it

transitions from logic high to logic low. This latches in the logic

levels on A0 and A1, resulting in a gain change. See the truth

table listing in Table 6 for more on these gain changes.

+15V

–15V

+IN

–IN

10μF0.1µF

DGND

REF

AD8251

+5V

G = PREVIOUS

STATE

G = 8

–

NOTE:

1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS

FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0

AND A1 ARE READ AND LATCHED IN, RESULTING IN A

GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 8.

Figure 51. Latched Gain Mode, G = 8

Table 6. Truth Table Logic Levels for Latched Gain Mode

Gain

High to Low

Low

Change to 1

High to Low

Low

High

Change to 2

High to Low

High

Low

Change to 4

High to Low

High

Change to 8

Low to Low

No Change

Low to High

No Change

High to High

No Change

1 X = don’t care.

On power-up, the AD8251 defaults to a gain of 1 when in

latched gain mode. In contrast, if the AD8251 is configured in

transparent gain mode, it starts at the gain indicated by the

voltage levels on A0 and A1 on power-up.

Timing for Latched Gain Mode

In latched gain mode, logic levels at A0 and A1 have to be held

for a minimum setup time, tSU, before the downward edge of

WR latches in the gain. Similarly, they must be held for a

minimum hold time of tHD after the downward edge of WR to

ensure that the gain is latched in correctly. After tHD, A0 and A1

may change logic levels but the gain does not change (until the

next downward edge of WR). The minimum duration that WR

can be held high is t WR-HIGH, and t WR-LOW is the minimum

duration that WR can be held low. Digital timing specifications

are listed in Table 2. The time required for a gain change is

dominated by the settling time of the amplifier. A timing

diagram is shown in Figure 52.

When sharing a data bus with other devices, logic levels applied

to those devices can potentially feed through to the output of

the AD8251. Feedthrough can be minimized by decreasing the

edge rate of the logic signals. Furthermore, careful layout of the

PCB also reduces coupling between the digital and analog

portions of the board.

A0, A1

tSU

tHD

tWR-HIGH

tWR-LOW

Figure 52. Timing Diagram for Latched Gain Mode

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