Philips Semiconductors

Product data

PCK2002

2001 Jul 19

4

DC CHARACTERISTICS

TEST CONDITIONS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

OTHER

MIN

MAX

HIGH level input voltage

3.135 to 3.465

2.0

V

LOW level input voltage

3.135 to 3.465

0.8

V

3 3V output HIGH voltage

3.135 to 3.465

—

V

3.3V output HIGH voltage

3.135

2.4

—

V

3 3V output LOW voltage

3.135 to 3.465

—

0.1

V

3.3V output LOW voltage

3.135

—

0.4

V

Output HIGH current

3.135

–54

–126

mA

Output HIGH current

3.465

–21

–46

mA

Output LOW current

3.135 to 3.465

49

118

mA

Output LOW current

3.135 to 3.465

24

53

mA

Input leakage current

3.465

—

±5

µA

3-State output OFF-State current

3.465

—

10

µA

Quiescent supply current

3.465

—

100

µA

Additional quiescent supply

current given per control pin

3.135 to 3.465

—

500

µA

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

SDRAM rise time

2, 4

1.5

2.0

4.0

V/ns

SDRAM fall time

2, 4

1.5

2.9

4.0

V/ns

SDRAM buffer LH propagation delay

4, 5

1.2

2.7

3.5

ns

SDRAM buffer HL propagation delay

4, 5

1.2

2.9

3.5

ns

SDRAM buffer enable time

4, 5

1.0

2.6

5.0

ns

SDRAM buffer disable time

4, 5

1.0

2.7

5.0

ns

DUTY CYCLE

Output Duty Cycle

Measured at 1.5 V

3, 4, 5

45

52

55

%

SDRAM Bus CLK skew

1, 4

—

150

250

ps

Device to device skew

—

—

500

ps

NOTES:

1. Skew is measured on the rising edge at 1.5 V.

3. Duty cycle should be tested with a 50/50% input.

4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5. Input edge rate for these tests must be faster than 1 V/ns.