| Electronic Components Datasheet Search |
|
WM8718SEDS/R Datasheet(PDF) 11 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8718SEDS/R Datasheet(HTML) 11 Page - Wolfson Microelectronics plc |
|
11 / 32 page ![]() WM8718 Production Data w PD Rev 4.3 November 2006 11 3-WIRE SERIAL CONTROL INTERFACE TIMING LATCH SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to LATCH rising edge tSCS 40 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 20 ns SCLK pulse width high tSCH 20 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns LATCH pulse width low tCSL 20 ns LATCH pulse width high tCSH 20 ns LATCH rising to SCLK rising tCSS 20 ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |