| Electronic Components Datasheet Search |
|
WM8591GEDS/V Datasheet(PDF) 21 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8591GEDS/V Datasheet(HTML) 21 Page - Wolfson Microelectronics plc |
|
21 / 51 page ![]() Production Data WM8591 w PD Rev 4.0 December 2005 21 DSP MODES In DSP/PCM mode, the left channel MSB is available on either the 1 st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. In device master mode, the LRC output will resemble the frame pulse shown in Figure 15 and Figure 16. In device slave mode, Figure 17 and Figure 18, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge of the next frame pulse. Figure 15 DSP/PCM Mode Audio Interface (mode A, LRP=0, Master) Figure 16 DSP/PCM Mode Audio Interface (mode B, LRP=1, Master) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |