ADT7408CCPZ-R2 datasheet(4/24 Pages) AD

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ADT7408

Rev. 0 | Page 4 of 24

TIMING CHARACTERISTICS

TA = −20°C to +125°C, VDD = 3.0 V to 3.6 V, unless otherwise noted.

Table 2.

Parameter1

Symbol

Min

Typ

Max

Unit

Comments

SCL Clock Frequency

fSCL

100

kHz

Bus Free Time Between a Stop (P) and Start (S) Condition

tBUF

4.7

μs

Hold Time After (Repeated) Start Condition

tHD:STA

4.0

μs

After this period, the first clock

is generated.

Repeated Start Condition Setup Time

tSU:STA

4.7

μs

High Period of the SCL Clock

tHIGH

4.0

μs

Low Period of the SCL Clock

tLOW

4.7

μs

Fall Time of Both SDA and SCL Signals

300

Rise Time of Both SDA and SCL Signals

1000

Data Setup Time

tSU:DAT

250

Data Hold Time

tHD:DAT

300

Setup Time for Stop Condition

tSU:STO

4.0

μs

Capacitive Load for Each Bus Line, CB

400

1 Guaranteed by design and characterization, not production tested.

TIMING DIAGRAM

SCL

SDA

VIH

tSU:DAT

tHIGH

tHD:DAT

tBUF

tLOW

tSU:STA

tSU:STO

tHD:STA

VIL

VIH

VIL

Figure 2. SMBus/I2C Timing Diagram

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