Nexperia

74LVC377

Octal D-type flip-flop with data enable; positive-edge trigger

Table 8. Measurement points

Supply voltage

Input

Output

VCC

VM

VM

1.2 V

0.5 × VCC

0.5 × VCC

1.65 V to 1.95V

0.5 × VCC

0.5 × VCC

2.3 V to 2.7 V

0.5 × VCC

0.5 × VCC

2.7 V

1.5 V

1.5 V

3.0 V to 3.6 V

1.5 V

1.5 V

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aaf615

VCC

VI

VO

DUT

CL

RT

RL

PULSE

GENERATOR

Test data is given in Table 9.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig. 6. Test circuit for switching times

Table 9. Test data

Input

Load

Supply voltage

VI

tr, tf

CL

RL

1.2 V

VCC

≤ 2 ns

30 pF

1 kΩ

1.65 V to 1.95 V

VCC

≤ 2 ns

30 pF

1 kΩ

2.3 V to 2.7 V

VCC

≤ 2 ns

30 pF

500 Ω

2.7 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500 Ω

74LVC377

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 7 — 27 August 2021

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