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ICS93705 Datasheet(PDF) 3 Page - Renesas Technology Corp

Part # ICS93705
Description  DDR Phase Lock Loop Zero Delay Clock Buffer
PDF  9 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS93705 Datasheet(HTML) 3 Page - Renesas Technology Corp

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3
ICS93705
0418D—04/28 /05
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
1
d
e
v
r
e
s
e
R
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B-
1
d
e
v
r
e
s
e
R
0
t
i
B-
1
d
e
v
r
e
s
e
R
Byte 3: Reserved
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
1
d
e
v
r
e
s
e
R
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B-
1
d
e
v
r
e
s
e
R
0
t
i
B-
1
d
e
v
r
e
s
e
R
Byte 4: Reserved
(1= enable, 0 = disable)
Byte 2: Reserved
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
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v
r
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s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
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v
r
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s
e
R
4
t
i
B-
1
d
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v
r
e
s
e
R
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B-
1
d
e
v
r
e
s
e
R
0
t
i
B-
1
d
e
v
r
e
s
e
R
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B2
,
31
)
C
&
T
(
0
K
L
C
6
t
i
B-
1
-
5
t
i
B9
,
0
11
)
C
&
T
(
2
K
L
C
4
t
i
B9
1
,
0
21
)
C
&
T
(
3
K
L
C
3
t
i
B3
2
,
2
21
)
C
&
T
(
4
K
L
C
2
t
i
B6
2
,
7
21
)
C
&
T
(
9
K
L
C
1
t
i
B-
1
d
e
v
r
e
s
e
R
0
t
i
B-
1
d
e
v
r
e
s
e
R
Byte 5: Reserved
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B0
3
,
9
21
)
C
&
T
(
8
K
L
C
3
t
i
B0
4
,
9
31
)
C
&
T
(
7
K
L
C
2
t
i
B3
4
,
4
41
)
C
&
T
(
6
K
L
C
1
t
i
B7
4
,
6
41
)
C
&
T
(
5
K
L
C
0
t
i
B-
1
d
e
v
r
e
s
e
R
Byte 6: Reserved
(1= enable, 0 = disable)
Note: Don’t write into these registers (7:5), writing into
these registers can cause malfunction.



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