5

Instructions

5.1

Write operations

Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The

device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each

address byte with an acknowledge bit, and then waits for the data byte.

Table 4. Most significant address byte

A15

A14

A13

A12

A11

A10

A9

A8

Table 5. Least significant address byte

A7

A6

A5

A4

A3

A2

A1

A0

The 256 Kbytes (2 Mb) are addressed with 18 address bits, the 16 lower address bits being defined by the two

address bytes and the most significant address bits (A17, A16) being included in the Device Select code (see

Table 4).

When the bus master generates a stop condition immediately after a data byte Ack bit (in the “10th bit” time slot),

either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any

other time slot does not trigger the internal write cycle.

After the stop condition and the successful completion of an internal write cycle (tW), the device internal address

counter is automatically incremented to point to the next byte after the last modified byte.

During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any

requests.

If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data

bytes are not acknowledged, as shown in Figure 8.

M24M02-DR M24M02-R

Instructions

DS7025 - Rev 11

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