SST26WF080BAT-104ISLASHCS datasheet(21/96 Pages) MICROCHIP

21 / 96 page

 2014-2017 Microchip Technology Inc.

DS20005283C-page 21

SST26WF040B/040BA SST26WF080B/080BA

FIGURE 5-12:

SET BURST LENGTH SEQUENCE (SPI)

5.10

SQI Read Burst with Wrap (RBSQI)

SQI Read Burst with wrap is similar to High Speed

Read in SQI mode, except data will output continuously

within the burst length until a low-to-high transition on

CE#. To execute a SQI Read Burst operation, drive

CE# low then send the Read Burst command cycle

(0CH), followed by three address cycles, and then

three dummy cycles. Each cycle is two nibbles (clocks)

long, most significant nibble first.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The data output stream is contin-

uous through all addresses until terminated by a low-to-

high transition on CE#.

During RBSQI, the internal address pointer automati-

cally increments until the last byte of the burst is

reached, then it wraps around to the first byte of the

burst. All bursts are aligned to addresses within the

burst length, see Table 5-3. For example, if the burst

length is eight Bytes, and the start address is 06h, the

burst sequence would be: 06h, 07h, 00h, 01h, 02h,

03h, 04h, 05h, 06h, etc. The pattern repeats until the

command is terminated by a low-to-high transition on

CE#.

During this operation, blocks that are Read-locked will

output data 00H.

5.11

SPI Read Burst with Wrap (RBSPI)

SPI Read Burst with Wrap (RBSPI) is similar to SPI

Quad I/O Read except the data will output continuously

within the burst length until a low-to-high transition on

CE#. To execute a SPI Read Burst with Wrap opera-

tion, drive CE# low, then send the Read Burst com-

mand cycle (ECH), followed by three address cycles,

and then three dummy cycles.

After the dummy cycle, the device outputs data on the

falling edge of the SCK signal starting from the speci-

fied address location. The data output stream is contin-

uous through all addresses until terminated by a low-to-

high transition on CE#.

During RBSPI, the internal address pointer automati-

cally increments until the last byte of the burst is

reached, then it wraps around to the first byte of the

burst. All bursts are aligned to addresses within the

burst length, see Table 5-3. For example, if the burst

length is eight Bytes, and the start address is 06h, the

burst sequence would be: 06h, 07h, 00h, 01h, 02h,

03h, 04h, 05h, 06h, etc. The pattern repeats until the

command is terminated by a low-to-high transition on

CE#.

During this operation, blocks that are Read-locked will

output data 00H.

CE#

SIO0

SCK

012345678

MODE 3

MODE 0

91011

20005283 F51.0

SIO[3:1]

13 14

DIN

Note: SIO[3:1] must be

TABLE 5-3:

BURST ADDRESS RANGES

Burst Length

Burst Address Ranges

8 Bytes

00-07H, 08-0FH, 10-17H, 18-1FH...

16 Bytes

00-0FH, 10-1FH, 20-2FH, 30-3FH...

32 Bytes

00-1FH, 20-3FH, 40-5FH, 60-7FH...

64 Bytes

00-3FH, 40-7FH, 80-BFH, C0-FFH

SST26WF080BAT-104I/CS Datasheet(PDF) 21 Page - Microchip Technology

SST26WF080BAT-104I/CS Datasheet(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL