Data Sheet

ADM3061E/ADM3062E/ADM3063E/ADM3064E/

ADM3065E/ADM3066E/ADM3067E/ADM3068E

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. H | 12 of 25

Figure 14. ADM3064E/ADM3068E 14-Lead SOIC_N Pin Configuration

Table 11. ADM3064E/ADM3068E Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VIO

1.62 V to 5.5 V Logic Supply. Adding a 0.1 µF decoupling capacitor between the VIO pin and the GND pin is recommended.

2

RO

Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is tristated when the receiver

is disabled, that is, when RE is driven high.

3

DE

Driver Enable. A high level on this pin enables the driver differential outputs, Y and Z. A low level places the driver output into a high

impedance state.

4

RE

Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high disables the receiver.

5

DI

Transmit Data Input. Data to be transmitted by the driver is applied to this input.

6, 8

GND

Ground.

7, 13

NIC

No Internal Connection. This pin is not internally connected.

9

Y

Driver Noninverting Output. When the driver is disabled, or when VCC is powered down, Pin Y is put into a high impedance state to avoid

overloading the bus.

10

Z

Driver Inverting Output. When the driver is disabled, or when VCC is powered down, Pin Z is put into a high impedance state to avoid

overloading the bus.

11

B

Inverting Receiver Input.

12

A

Noninverting Receiver Input.

14

VCC

3.0 V to 5.5 V Power Supply. Adding a 0.1 µF decoupling capacitor between the VCC pin and the GND pin is recommended.