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FT81X Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000002 Clearance No.: BRT#004

From the SLEEP state, the host MPU sends an SPI ACTIVE command to wake the FT81x into the ACTIVE

state. The host needs to wait for at least 20ms before accessing any registers or commands. This is to

guarantee the clock oscillator and PLL are up and stable.

From the STANDBY state, the host MPU sends SPI ACTIVE command to wake the FT81x into the ACTIVE

state. The host can immediately access any register or command.

4.8.4

Reset and boot-up sequence

There are a few hardware and software reset events which can be triggered to reset the FT81x.

Hardware reset events:



Power-on-Reset(POR)



Toggle the PD_N pin

Software reset events:



SPI command RST_PULSE



SPI command to switch between the internal clock and the external clock



SPI command to enter POWERDOWN then wakeup

After reset the FT81x will be in the SLEEP state. Upon receiving an SPI ACTIVE command, the internal

oscillator and PLL will start up. Once the clock is stable, the chip will check and repair its internal RAM,

running the configuration and release the clock to the system. The chip will exit the reset and boot-up

state and enter into normal operations. The boot-up may take up to 300ms to complete.

4.8.5

Pin Status at Different Power States

The FT81x pin status depends on the power state of the chip. See the following table for more details. At

the power transition from ACTIVE to STANDBY or ACTIVE to SLEEP, all pins retain their previous status.

The software needs to set AUDIO_L, BACKLIGHT to a known state before issuing power transition

commands.

The pin status in the power down state can be changed by SPI command PIN_PD_STATE.

Pin Name

Default Drive

Reset

Normal

Power Down

(Default)

AUDIO_L

20mA

Out, Float

Out

Pull Low

SCK

MISO

5mA

Out, Float

(CS_N = 1)

Out, Float

MOSI

5mA

CS_N

IO2

GPIO0

5mA

Float

IO3

GPIO1

5mA

Float

GPIO2

5mA

Float

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