AM2432...ALV datasheet(198/280 Pages) TI

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7.10.5.12.1.2 High Speed SDR Mode

Table 7-70, Figure 7-60, Table 7-71, and Figure 7-61 present timing requirements and switching characteristics

for MMC0 – High Speed SDR Mode.

Table 7-70. MMC0 Timing Requirements – High Speed SDR Mode

see Figure 7-60

NO.

MIN

MAX

UNIT

HSSDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

2.99

HSSDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

2.67

HSSDR3

tsu(dV-clkH)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge

2.99

HSSDR4

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

2.67

Figure 7-60. MMC0 – High Speed SDR Mode – Receive Mode

Table 7-71. MMC0 Switching Characteristics – High Speed SDR Mode

see Figure 7-61

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSSDR5

tc(clk)

Cycle time, MMC0_CLK

HSSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

-6.35

6.35

HSSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

-6.35

6.35

Figure 7-61. MMC0 – High Speed SDR Mode – Transmit Mode

AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

www.ti.com

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