AM2432...ALV datasheet(197/280 Pages) TI

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7.10.5.12.1.1 Legacy SDR Mode

Table 7-68, Figure 7-58, Table 7-69, and Figure 7-59 present timing requirements and switching characteristics

for MMC0 – Legacy SDR Mode.

Table 7-68. MMC0 Timing Requirements – Legacy SDR Mode

see Figure 7-58

NO.

MIN

MAX

UNIT

LSDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

9.69

LSDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

27.97

LSDR3

tsu(dV-clkH)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge

9.69

LSDR4

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

27.97

Figure 7-58. MMC0 – Legacy SDR – Receive Mode

Table 7-69. MMC0 Switching Characteristics – Legacy SDR Mode

see Figure 7-59

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

LSDR5

tc(clk)

Cycle time, MMC0_CLK

LSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

18.7

LSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

18.7

LSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

-16.1

16.1

LSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

-16.1

16.1

Figure 7-59. MMC0 – Legacy SDR – Transmit Mode

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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