TLV9041UIDBVR datasheet(10/61 Pages) TI

10 / 61 page

7.7 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at TA = 25°C, RL = 100 kΩ connected to VS / 2, VCM = VS / 2, and

VO UT = VS / 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EMIRR

Electro-magnetic

interference rejection

ratio

f = 1 GHz, VIN_EMIRR = 100 mV

OUTPUT

Voltage output swing

from rail

Positive rail headroom

VS = 1.2 V,

RL = 100 kΩ to VS / 2

0.75

VS = 5.5 V,

RL = 10 kΩ to VS / 2

VS = 5.5 V,

RL = 100 kΩ to VS / 2

Negative rail headroom

VS = 1.2 V,

RL = 100 kΩ to VS / 2

0.75

VS = 5.5 V,

RL = 10 kΩ to VS / 2

VS = 5.5 V,

RL = 100 kΩ to VS / 2

ISC

Short-circuit current (4) VS = 5.5 V

±40

Open-loop output

impedance

f = 10 kHz

7500

Ω

POWER SUPPLY

Quiescent current per

amplifier

VS = 5.5 V, IO = 0 A

µA

TA = –40°C to 125°C

13.5

Quiescent current per

amplifier

VS = 5.5 V, IO = 0 A, For TLV9041UIDBVR Only

13.5

µA

TA = –40°C to 125°C

µA

SHUTDOWN

IQSD

Quiescent current per

amplifier

All amplifiers disabled, SHDN = V–

200

ZSHDN

Output impedance

during shutdown

Amplifier disabled

43 || 11.5

GΩ || pF

VIH

Logic high threshold

voltage (amplifier

enabled)

(V–) + 1 V

VIL

Logic low threshold

voltage (amplifier

disabled)

(V–) + 0.2

tON

Amplifier enable time

(full shutdown) (5) (6)

G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–

160

µs

Amplifier enable time

(partial shutdown)

(5) (6)

G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V–

120

tOFF

Amplifier disable time

(5)

G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V–

µs

SHDN pin input bias

current (per pin)

(V+) ≥ SHDN ≥ (V–) + 1 V

100

(V–) ≤ SHDN ≤ (V–) + 0.2 V

(1)

Max IB and IOS limits are specified based on characterization results. Input differential voltages greater than 2.5V can cause increased

(2)

Typical input current noise data is specified based on design simulation results

(3)

Third-order filter; bandwidth = 80 kHz at –3 dB.

(4)

Short circuit current is average of sourcing and sinking short circuit currents

(5)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(6)

Full shutdown refers to the dual TLV9042S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9044S

having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode,

the internal biasing circuitry remains operational and the enable time is shorter.

TLV9041, TLV9042, TLV9044

SBOS836G – MARCH 2020 – REVISED MARCH 2022

www.ti.com

Submit Document Feedback

Product Folder Links: TLV9041 TLV9042 TLV9044

TLV9041UIDBVR Datasheet(PDF) 10 Page - Texas Instruments

TLV9041UIDBVR Datasheet(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL