STM32L072KB datasheet(34/160 Pages) STMICROELECTRONICS

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Functional overview

STM32L072xx

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DS10689 Rev 5

independent from the CPU clock, allowing the I2C1/I2C3 to wake up the MCU from Stop

mode on address match.

Each I2C interface can be served by the DMA controller.

Refer to Table 12 for an overview of I2C interface features.

3.17.2

Universal synchronous/asynchronous receiver transmitter (USART)

The four USART interfaces (USART1, USART2, USART4 and USART5) are able to

communicate at speeds of up to 4 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 driver enable (DE)

signals, multiprocessor communication mode, master synchronous communication and

single-wire half-duplex communication mode. USART1 and USART2 also support

SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto

baud rate feature and has a clock domain independent from the CPU clock, allowing to

wake up the MCU from Stop mode using baudrates up to 42 Kbaud.

All USART interfaces can be served by the DMA controller.

Table 13 for the supported modes and features of USART interfaces.

Table 12. STM32L072xx I2C implementation

I2C features(1)

1. X = supported.

I2C1

I2C2

I2C3

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20 mA output drive I/Os (up to 1

Mbit/s)

XX(2)

2. See Table 16: STM32L072xxx pin definition on page 44 for the list of I/Os that feature Fast Mode Plus

capability

Independent clock

SMBus

Wakeup from STOP

Table 13. USART implementation

USART modes/features(1)

USART1 and USART2 USART4 and USART5

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode(2)

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

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