MPC8343ECVRADDB datasheet(13/80 Pages) NXP

13 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and

electrical requirements of the MPC8343EA.

5.1

RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8343EA.

EC_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

EC_GTX_CLK125 jitter

—

±150

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for

LVDD =3.3 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125

duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T

reference clock.

Table 9. RESET Pins DC Electrical Characteristics1

Parameter

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

——

±5

μA

Output high voltage2

VOH

IOH = –8.0 mA

2.4

—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.

Table 8. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV (continued)

Parameter

Symbol

Min

Typical

Max

Unit

Notes

MPC8343ECVRADDB Datasheet(PDF) 13 Page - NXP Semiconductors

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