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PL123-09SI-R Datasheet(PDF) 1 Page - Micrel Semiconductor |
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PL123-09SI-R Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 9 page  PL123-05/-09 Low Skew Zero Delay Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/22/13 Page 1 FEATURES Frequency Range 10MHz to 134 MHz Output Options: o 5 outputs PL123-05 o 9 outputs PL123-09 Zero input - output delay Optional Drive Strength: Standard (8mA) PL123-05/-09 High (12mA) PL123-05H/-09H 3.3V, ±10% operation Available in Commercial and Industrial temperature ranges Available in 16-Pin SOP or TSSOP (PL123-09), and 8-Pin SOP (PL123-05) packages DESCRIPTION The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propaga- tion delay can be advanced or delayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input-tolerant ap- plications. BLOCK DIAGRAM PLL REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 Mux CLKB1 CLKB2 CLKB3 CLKB4 S1 S2 1 REF CLKA1 CLKA2 VDD CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 10 11 12 13 14 15 16 9 8 7 6 5 4 3 2 S2 CLKB2 CLKB1 GND Selector Inputs (PL123-09 Only) 1 2 3 4 REF 5 6 7 8 CLKA2 CLKA1 GND CLKOUT CLKA4 VDD CLKA3 |
Similar Part No. - PL123-09SI-R |
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Similar Description - PL123-09SI-R |
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