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STPD01 Datasheet(PDF) 22 Page - STMicroelectronics

Part # STPD01
Description  Programmable buck converter for USB power delivery
PDF  43 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPD01 Datasheet(HTML) 22 Page - STMicroelectronics

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7.11
Pulse skip
At light loads, the device works in discontinuous conduction mode. Zero-cross comparator is implemented to
detect when the coil current crosses the zero during TOFF (i.e. low-side MOSFET on). During the sleep periods of
the DCM operations both power MOSFETs are off and the efficiency is improved according to that. Moreover, the
sleep period is a function of the load.
Since the device works at almost fixed frequency (only 500 kHz or 750 kHz are selectable by I2C) with fixed
minimum Ton typically 100 ns and wide PVIN range, up to 26.4 V, pulse skipping operation occurs to guarantee
the proper regulation to light load (or no load conditions).
In addition, the pulse skip threshold (i.e. the voltage the device enters the pulse skip operation) can be properly
selected to optimize the efficiency at light loads.
7.12
Bus timing
As shown in the figure below, the data on the SDA line must be stable during the high semi-period of the clock.
The high and low-state of the data line can only change when the clock signal on the SCL line is low.
Figure 37. Data transfer validity
SDA
SCL
Data line stable
Data valid
Data change
allowed
Each bus transaction begins with a “START” command which is defined as SDA transition from 1 to 0 with SCL
high, and it is finished with a “STOP” command, which is defined as SDA transition from 0 to 1 with SCL high, as
shown in Figure 38. START and STOP commands.
Figure 38. START and STOP commands
Stop
Condition
Start
Condition
SDA
SCL
The master generates the start command and transmits the 7-bit address and the read/write bit on SDA line. All
slave devices compare the address sent by the master to their internal fixed addresses. Only the slave device,
with a matching address, generates an ACK by pulling the SDA line low during the entire high period of the ninth
SCL clock. The acknowledge bit is used to indicate a successful byte transfer.
STPD01
Pulse skip
DS13473 - Rev 1
page 22/43



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