CS42418 datasheet(21/67 Pages) CIRRUS

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CS42418

3.5.3

ADCIN1/ADCIN2 Serial Data Format

The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support

only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port

configuration register bit settings. These serial data lines are used when supporting One Line Mode of op-

eration with external ADCs attached. If these signals are not being used, they should be tied together and

wired to GND via a pull-down resistor.

For proper operation, the CS42418 must be configured to select which SCLK/LRCK is being used to clock

the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 36, must

be set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs

are wired to use the ADC_SP clocks, set this bit to ‘0’.

DA C_LRCK

A DC_LRCK

DA C_S CLK

A DC_S CLK

Left Chann el

R igh t Chan nel

A DCIN1/2

+3 +2 +1

+5 +4

-1 -2 -3 -4 -5

+3 +2 +1

+5 + 4

-1 -2 -3 -4

MSB

LS B

MSB

L SB

Figure 12. ADCIN1/ADCIN2 Serial Audio Format

Left Justified Mode, Data Valid on Rising Edge of SCLK

Bits/Sample

SCLK Rate(s)

Notes

64, 128 Fs

single-speed mode, Fs= 32, 44.1, 48 kHz

64 Fs

double-speed mode, Fs= 64, 88.2, 96 kHz

not supported

quad-speed mode, Fs= 176.4, 192 kHz

CS42418 Datasheet(PDF) 21 Page - Cirrus Logic