CS5321 datasheet(21/36 Pages) CIRRUS

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CS5321/22

DS454F2

must have less than 300 ps jitter to maintain data

sheet performance from the device. The CS5321 is

equipped with loss of clock detection circuitry

which will cause the CS5321 to enter a powered-

down state if the MCLK is removed or reduced to

a very low frequency. The HBR pin on the CS5321

modifies the sampling clock rate of the modulator.

When HBR = 1, the modulator sampling clock will

be at MCLK/4; with HBR = 0 the modulator sam-

pling clock will be at MCLK/8. The chip set will ex-

hibit about 3 dB less S/N performance when the

HBR pin is changed from a logic "1" to a logic "0"

for the same output word rate from the CS5322.

2.6 Low Power Mode

The CS5321 includes a low power operating mode

(LPWR =1). When operated with LPWR = 1, the

CS5321 modulator sampling clock must be restrict-

ed to rates of 128 kHz or less. Operating in low

power mode with modulator sample rates greater

than 128 kHz will greatly degrade performance.

2.7 Digital Interface and Data Format

The MCLK signal (normally 1.024 MHz) is divid-

ed by four, or by eight inside the CS5321 to gener-

ate the modulator oversampling clock. The HBR

pin determines whether the clock divider inside the

CS5321 divides by four (HBR =1) or by eight

(HBR = 0). The modulator outputs a ones density

bit stream from its MDATA and MDATA pins pro-

portional to the analog input signal, but at a bit rate

determined by the modulator over sampling clock.

For proper synchronization of the bitstream, the

CS5321 must be furnished with an MSYNC signal

prior to data conversion. The MSYNC signal, gen-

erated by the CS5322, resets the MCLK counter-di-

vider in the CS5321 to the correct phase so that the

bitstream can be properly sampled by the CS5322

digital filter.

When operated with the CS5322 digital filter the

output codes from the CS5321/22 will range from

approximately decimal -5,242,880 to +5,242,879

for an input to the CS5321 of

±4.5 V. Table 1 illus-

trates the output coding for various input signal am-

plitudes. Note that with a signal input defined as a

full scale signal (4.5 V with VREF+ = 4.5 V) the

CS5321/22 chipset does not output a full scale dig-

ital code of 8,388,607 but is scaled to a lower value

to allow some overrange capability. Input signals

can exceed the defined full scale by up to 5% and

still be converted properly.

Modulator Input

Signal

CS5322 Filter

Output Code

HEX

Decimal

> (+VREF + 5%)

Error Flag Possible

≈ (+VREF + 5%)

53FFFF(H)

+5505023

+VREF

4FFFFF(H)

+5242879

000000(H)

-VREF

B00000(H)

-5242880

≈ - (+VREF +5%)

AC0000(H)

-5505024

> - (+VREF +5%)

Error Flag Possible

Table 1. Output Coding for the CS5321 and

CS5322 Combination

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