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WM8802SCFV Datasheet(PDF) 45 Page - Wolfson Microelectronics plc |
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WM8802SCFV Datasheet(HTML) 45 Page - Wolfson Microelectronics plc |
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45 / 65 page ![]() Product Preview WM8802 w PP Rev 1.1 April 2004 45 S system output clock setting: REGISTER ADDRESS DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 1 0 0 0 0 CAU CAL DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 CCB address: 0xE8; Command address: 4 XSLRCK1 XSLRCK0 XSBCK1 XSBCK0 PSLRCK1 PSLRCK0 PSBCK1 PSBCK0 PSBCK [1:0] SBCK frequency setting during PLL lock 00: 64fs output (initial value) 01: 128fs output 10: 32fs output 11: Muted PSLRCK [1:0] SLRCK frequency setting during PLL lock 00: fs output (initial value) 01: 2fs output 10: fs/2 output 11: Muted XSBCK [1:0] SBCK frequency setting during XIN source 00: 3.072MHz output (initial value) 01: 6.144MHz output 10: 12.288MHz output 11: Muted XSLRCK [1:0] SLRCK frequency setting during XIN source 00: 48kHz output (initial value) 01: 96kHz output 10: 192kHz output 11: Muted |
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