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G682L18SQL1U Datasheet(PDF) 14 Page - Global Mixed-mode Technology Inc |
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G682L18SQL1U Datasheet(HTML) 14 Page - Global Mixed-mode Technology Inc |
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14 / 18 page  Ver: 0.8 Feb 27, 2013 TEL: 886-3-5788833 http://www.gmt.com.tw 14 G682/G683 Global Mixed-mode Technology Ensuring a Valid Reset Output Down to VCC = 0V When VCC falls below 0.8V, the G682 RESET output no longer sinks current and it becomes an open circuit. Therefore, high-impedance CMOS logic inputs con- nected to RESET can drift to undetermined voltages. This presents no problem in most applications since most μP and other circuitry is inoperative with VCC be- low 0.8V. However, in applications where RESET must be valid down to 0V, adding a pull-down resistor to RESET causes any stray leakage currents to flow to ground, holding RESET low (Figure 4). R1’s value is not critical; 100k Ω is large enough not to load RESET and small enough to pull RESET to ground. A 100k Ω pull-up resistor to VCC is also recommended for the G683L if RESET is required to remain valid for VCC < 0.8V. Figure 4 G683L Open-Drain RESET Output Allows Use with Multiple Supplies Generally, the pull-up connected to the G683L will connect to the supply voltage that is being monitored at the IC’s VCC pin. However, some systems may use the open-drain output to level-shift from the monitored sup- ply to reset circuitry powered by some other supply (Figure 5). Note that as the G683L’s VCC decreases below 1V, so does the IC’s ability to sink current at RESET . Also, with any pull-up, RESET will be pulled high as VCC decays toward 0. The voltage where this occurs depends on the pull-up resistor value and the voltage to which it is connected. Figure 5 VCC RESET GND G682 R1 100k VSEN VCC RESET GND G682 R1 100k VSEN RESET INPUT GND 5V SYSTEM RESET GND G683 RPULL-UP RESET INPUT GND 5V SYSTEM VCC RPULL-UP VCC 5V 3.3V VSEN Detect Voltage RESET INPUT GND 5V SYSTEM RESET GND G683 RPULL-UP RESET INPUT GND 5V SYSTEM VCC RPULL-UP VCC 5V 3.3V VSEN Detect Voltage |
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