GD5F1GQ4UFFJS datasheet(21/59 Pages) GIGADEVICE

Part #	GD5F1GQ4UFFJS

Description	SPI(x1/x2/x4) NAND Flash

PDF	59 Pages

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Manufacturer	GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]

Direct Link	http://www.gigadevice.com/

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21 / 59 page

SPI(x1/x2/x4) NAND Flash

9.7 Read From Cache Dual IO (BBH)

The Read from Cache Dual I/O command (BBH) is similar to the Read form Cache x2 command (3BH), followed by a 12bit

column address for the starting byte address and a dummy byte by SIO0 and SIO1, each bit being latched in during the

rising edge of SCLK, then the cache contents are shifted out 2-bit per clock cycle from SIO0 and SIO1. The first address

byte can be at any location. The address increments automatically to the next higher address after each byte of data shifted

out until the end of whole page.

Figure9-6. Read From Cache Dual IO Sequence Diagram

Command

0 1 2 3 4 5 6 7

BBH

CS#

SCLK

SI(SIO0)

SO(SIO1)

8 9 10 11 12 13 14 15

6 4 2 0 6 4 2 0

16 17 18 19 20 21 22 23

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

A7-0

Dummy

Byte0

CS#

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SI(SIO0)

SO(SIO1)

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

SCLK

Byte1

Byte2

Byte3

Byte4

Dummy, A11-8

GD5F1GQ4UFFJS Datasheet(PDF) 21 Page - GigaDevice Semiconductor (Beijing) Inc.