AD9739-R2-EBZ datasheet(7/50 Pages) AD

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Data Sheet

AD9739

Rev. E | Page 7 of 50

SERIAL PORT SPECIFICATIONS

VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V.

Table 3.

Parameter

Min

Typ

Max

Unit

WRITE OPERATION (See Figure 36)

SCLK Clock Rate, f

SCLK (or /tSCLK)

MHz

SCLK Clock High, t

SCLK Clock Low, t

LOW

SDIO to SCLK Setup Time, t

SCLK to SDIO Hold Time, t

CS to SCLK Setup Time, t

SCLK to CS Hold Time, t

READ OPERATION (See Figure 37 and Figure 38)

SCLK Clock Rate, f

SCLK (or /tSCLK)

MHz

SCLK Clock High, t

SCLK Clock Low, t

LOW

SDIO to SCLK Setup Time, t

SCLK to SDIO Hold Time, t

CS to SCLK Setup Time, t

SCLK to SDIO (or SDO) Data Valid Time, t

CS to SDIO (or SDO) Output Valid to High-Z, t

INPUTS (SDIO, SCLK, CS)

Voltage in High, V

2.0

3.3

Voltage in Low, V

0.8

Current in High, I

−10

+10

µA

Current in Low, I

−10

+10

µA

OUTPUT (SDIO)

Voltage Out High, V

2.4

3.5

Voltage Out Low, V

0.4

Current Out High, I

Current Out Low, I

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