WM8718

Production Data

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PD Rev 4.1 March 2004

12

DSP EARLY MODE

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that

detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words.

The word order is DIN left, DIN right.

LRCIN

BCKIN

DIN

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCKIN

1 BCKIN

Figure 7 DSP Early Mode Timing Diagram

DSP LATE MODE

In DSP late mode, the first bit is sampled on the BCKIN rising edge, which detects a low to high

transition on LRCIN. No BCKIN edges are allowed between the data words. The word order is

DIN left, DIN right.

LRCIN

BCKIN

DIN

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1

Figure 8 DSP Late Mode Timing Diagram

AUDIO DATA SAMPLING RATES

The master clock for WM8718 can range from 128fs to 768fs where fs is the audio sampling

frequency (LRCIN), typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used

to operate the digital filters and the noise shaping circuits.

The WM8718 has a master clock detection circuit that automatically determines the relationship

between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If

there is greater than 32 clocks error, the system will default to 768fs. The master clock should be

synchronised with LRCIN, although the WM8718 is tolerant of phase differences or jitter on this

clock. See Table 1.