Product Description
The PI6C2302 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver. By connecting the feedback CLK_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. The PI6C2302 provides 2X CLK_IN on CLK_OUT output.

Product Features
• 2X CLK_IN on CLK_OUT
• High-Performance Phase-Locked-Loop Clock Distribution
   for Networking, ATM, 100/134 MHz Registered DIMM
   Synchronous DRAM modules for server/workstation/
   PC applications
• Zero Input-to-Output delay
• Low jitter: Cycle-to-Cycle jitter –100ps max.
• On-chip series damping resistor at clock output drivers
   for low noise and EMI reduction
• Operates at 3.3V VCC
• Wide range of Clock Frequencies
• Package:
   Plastic 8-pin SOIC Package (W)