Overview The DSCC4 is a DMA Supported Serial Communication Controller with four independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC device family providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications. Features Serial Communication Controllers (SCCs) • Four independent channels • Full duplex data rates on each channel of up to 10 Mbit/s sync - 2 Mbit/s with DPLL, 2 Mbit/s async • Full duplex data rate of up to 52 Mbit/s on any two channels in high speed mode (HDLC: Address Mode 0 and extended transparent protocol mode); up to 45 Mbit/s on any two channels in high speed mode (HDLC: PPP modes). The aggregate bandwith for all channels is limited to 108 Mbit/s per direction. • 17 DWORDs deep receive FIFO per SCC (+ 128 DWORDs central receive FIFO). • 8 DWORDs deep transmit FIFO per SCC (+ 128 DWORDs central transmit FIFO). Serial Interface • On-chip clock generation or external clock sources • On-chip DPLLs for clock recovery • Baud rate generator • Clock gating signals • Clock gapping capability • Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1) • NRZ, NRZI, FM and Manchester data encoding • Optional data flow control using modem control lines (RTS, CTS, CD) • Support of bus configuration by collision detection and resolution • HDLC/SDLC Protocol Modes – Automatic flag detection and transmission – Shared opening and closing flag – Generation of interframe-time fill ’1’s or flags – Detection of receive line status – Zero bit insertion and deletion – CRC generation and checking (CRC-CCITT or CRC-32) – Transparent CRC option per channel and/or per frame – Programmable Preamble (8 bit) with selectable repetition rate – Error detection (abort, long frame, CRC error, short frames) • Bit Synchronous PPP Mode – Bit oriented transmission of HDLC frame (flag, data, CRC, flag) – Zero bit insertion/deletion – 15 consecutive ’1’ bits abort sequence • Octet Synchronous PPP Mode – Octet oriented transmission of HDLC frame (flag, data, CRC, flag) – Programmable character map of 32 hard-wired characters (00H-1FH) – Four programmable characters for additional mapping – Insertion/deletion of control-escape character (7DH) for mapped characters • Asynchronous PPP Mode – Character oriented transmission of HDLC frame (flag, data, CRC, flag) – Start/stop bit framing of single character – Programmable character map of 32 hard-wired characters (00H-1FH) – Four programmable characters for additional mapping – Insertion/deletion of control-escape character (7DH) for mapped characters • Asynchronous (ASYNC) Protocol Mode – Selectable character length (5 to 8 bits) – Even, odd, forced or no parity generation/checking – 1 or 2 stop bits – Break detection/generation – In-band flow control by XON/XOFF – Immediate character insertion – Termination character detection for end of block identification – Time out detection – Error detection (parity error, framing error) • BISYNC Protocol Mode – Programmable 6/8 bit SYN pattern (MONOSYNC) – Programmable 12/16 bit SYN pattern (BISYNC) – Selectable character length (5 to 8 bits) – Even, odd, forced or no parity generation/checking – Generation of interframe-time fill ’1’s or SYN characters – CRC generation (CRC-16 or CRC-CCITT) – Transparent CRC option per channel and/or per frame (Continue ...)
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