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Summary of Features • High Performance 16-bit CPU with 4-Stage Pipeline – 80 ns Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit) – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to Support HLL and Operating Systems – Register-Based Design with Multiple Variable Register Banks – Single-Cycle Context Switching Support – 16 Mbytes Total Linear Address Space for Code and Data – 1024 Bytes On-Chip Special Function Register Area • 16-Priority-Level Interrupt System with 30 Sources, Sample-Rate down to 40 ns • 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) • Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input • On-Chip Memory Modules: 2 Kbytes On-Chip Internal RAM (IRAM) • On-Chip Peripheral Modules – Two Multi-Functional General Purpose Timer Units with 5 Timers – Two Serial Channels (Sync./Asynchronous and High-Speed-Synchronous) – On-Chip Real Time Clock • External Address Space for Code and Data – Programmable External Bus Characteristics for Different Address Ranges – Multiplexed or Demultiplexed External Address/Data Buses with 8-bit or 16-bit Data Bus Width – Four Programmable Chip-Select Signals – 4 Mbytes maximum address window size, results in a total external address space of 16 Mbytes, when all chip-select signal (address windows) are active • Idle and Power Down Modes with Flexible Power Management • Programmable Watchdog Timer and Oscillator Watchdog • Up to 63 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis • Power Supply: the C161S can operate from a 5 V or a 3 V power supply (see Table 1) • Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards • On-Chip Bootstrap Loader • 80-Pin MQFP Package
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