120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory,
512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC,
full-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D
converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface

■ 32-bit RXv2 CPU core
 Max. operating frequency: 120 MHz
Capable of 240 DMIPS in operation at 120 MHz
 Single precision 32-bit IEEE-754 floating point
 Two types of multiply-and-accumulation unit (between memories
and between registers)
 32-bit multiplier (fastest instruction execution takes one CPU clock
cycle)
 Divider (fastest instruction execution takes two CPU clock cycles)
 Fast interrupt
 CISC Harvard architecture with 5-stage pipeline
 Variable-length instructions: Ultra-compact code
 Supports the memory protection unit (MPU)
 JTAG and FINE (one-line) debugging interfaces
■ Low-power design and architecture
 Single voltage supply: 2.7 to 3.6 V
 Low power consumption: A product that supports all peripheral
functions draws only 0.3mA/MHz (Typ.).
 RTC is capable of operation from a dedicated power supply.
 Four low-power modes