Ultra-low power consumption technology
 VDD = single power supply voltage of 1.8 to 5.5 V which
can operate at a low voltage
 HALT mode
 STOP mode
 SNOOZE mode
RL78 CPU core
 CISC architecture with 3-stage pipeline
 Minimum instruction execution time: Can be changed
from high speed (0.04167 s: @ 24 MHz operation with
high-speed on-chip oscillator) to ultra-low speed (1 s:
@ 1 MHz operation)
 Address space: 1 MB
 General-purpose registers: (8-bit register x 8) x 4 banks
 On-chip RAM: 256 B to 2 KB
Code flash memory
 Code flash memory: 2 to 16 KB
 Block size: 1 KB
 Prohibition of block erase and rewriting (security
function)
 On-chip debug function
 Self-programming (with flash shield window function)
Data flash memory Note2
 Data flash memory: 2 KB
 Back ground operation (BGO): Instructions are
executed from the program memory while rewriting the
data flash memory.
 Number of rewrites: 1,000,000 times (TYP.)
 Voltage of rewrites: VDD = 1.8 to 5.5 V