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description
The 107 contain two independent JK flip-flops with
individual JK, clock, and direct clear inputs. The ‘107
is a positive pulse-triggered flip-flop. The J-K input data
is loaded into the master while the clock is high and
transferred to the slave and the outputs on the high-to-
low clock transistion. For these devices the J and K inputs
must be stable while the clock is high.
The 'LS107A contain two independent negative-edge-
triggered flip-flops. The J and K inputs must be stable
prior to the high-to-low clock transition for predictable
operation. When the clear is low, it overrides the clock
and data inputs forcing the Q output low and the Q
output high.
The SN54107 and the SN54LS107A are characterized
for operation over the full military temperature range of
~55°C to 125°C. The SN74107 and the SN74LS107A
are characterized for operation from 0°C to 70°C.