1 Features
• SCR-Latch-up-resistant CMOS process and circuit
design
• Speed of bipolar FAST*/AS/S with significantly
reduced power consumption
• Balanced propagation delays
• AC types feature 1.5V to 5.5V operation and
balanced noise immunity at 30% of the supply
• ± 24mA output drive current
– Fanout to 15 FAST* ICs
– Drives 50ohm transmission lines

2 Description
The eight flip-flops of the ’AC374 devices are D-type
edge-triggered flip-flops. On the positive transition of
the clock (CLK) input, the Q outputs are set to the
logic levels set up at the data (D) inputs.