1FEATURES
· Differential PECL/NECL Receiver
· Operating Range
– PECL: VCC = 4.2 V to 5.7 V With VEE = 0 V
– NECL: VCC = 0 V With VEE = –4.2 V to –5.7 V
· 250-ps Propagation Delay
· Support for Clock Frequencies >2 GHz
· Deterministic Output Value for Open Input
Conditions
· Built-In Temperature Compensation
· Drop-In Compatible With MC10EL16,
MC100EL16
· Built-In Input Pulldown Resistors

APPLICATIONS
· Data and Clock Transmission Over Backplane

DESCRIPTION
The SN65EL16 is a differential PECL/ECL receiver
with PECL/ECL output. The device includes circuitry
to hold Q to a low logic level when the inputs are in
an open condition.
The VBB pin is a reference voltage output for the
device. When the device is used in the single-ended
mode, the unused input should be tied to VBB. This
reference voltage can also be used to bias the input
when it is ac coupled. When the VBB pin is used,
place a 0.01-mF decoupling capacitor between VCC
and VBB. Also, limit the sink/source current to <0.5
mA to VBB. Leave VBB open when it is not used.
The SN65EL11 is housed in an industry-standard
SOIC-8 package and is also available in a TSSOP-8
package.