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PM5352 Datasheet (PDF) - PMC-Sierra, Inc

PM5352 Datasheet PDF - PMC-Sierra, Inc
Part # PM5352
Download  PM5352 Download

File Size   57.29 Kbytes
Page   2 Pages
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc
Description 155 Mbit/s ATM and Packet-Over-SONET/SDH Physical Layer Device

PM5352 Datasheet (PDF)

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PM5352 Datasheet PDF - PMC-Sierra, Inc

Part # PM5352
Download  PM5352 Click to download

File Size   57.29 Kbytes
Page   2 Pages
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc
Description 155 Mbit/s ATM and Packet-Over-SONET/SDH Physical Layer Device

PM5352 Datasheet (HTML) - PMC-Sierra, Inc

PM5352 Datasheet HTML 1Page - PMC-Sierra, Inc PM5352 Datasheet HTML 2Page - PMC-Sierra, Inc

PM5352 Product details

DATASHEET OVERVIEW
The PM5352 S/UNI-STAR is functionally equivalent to a single channel PM5351 S/UNI-TETRA (TETRA channel #4). The devices are software compatible and pin compatible. This datasheet provides a complete pinout description for the S/UNI-STAR, as well as any differences between these devices (including boundary scan register, test mode 0 register). For a complete functional and register description, please refer to the PMC-971240.

FEATURES
General
• Single chip ATM User-Network Interface operating at 155.52 Mbit/s.
• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).
• Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip clock and data recovery and clock synthesis.
• Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
• Exceeds Bellcore GR-253-CORE jitter transfer and phase variation criteria.
• Provides control circuitry required to exceed Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
• Compatible with ATM Forum’s Utopia Level 2 Specification with MultiPHY addressing and parity support.
• Implements the POS-PHY 16-bit System Interface for Packet over SONET/SDH (POS) applications. This system interface is similar to Utopia Level 2, but adapted to packet transfer. Both byte-level and packet-level transfer modes are supported.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power 3.3V CMOS with PECL and TTL compatible inputs and CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V only).
• Industrial temperature range (-40°C to +85°C).
• 304 pin Super BGA package.

APPLICATIONS
• DSLAM uplinks
• Access Concentrators
• WAN and edge ATM switches.
• LAN switches and hubs.
• Layer 3 switches.
• Multiservice switches (FR, ATM, IP, etc..).




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