Features
• Four differential LVDS output pairs
• Selectable differential CLK/nCLK or LVPECL clock inputs
• CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• PCLK/nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
• Additive phase Jitter, RMS: 0.164ps (typical)
• Output skew: 40ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Propagation delay: 2.6ns (maximum)
• Full 3.3Vsupply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages