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M5M5256DFP-70LLI Datasheet(PDF) 6 Page - Renesas Technology Corp |
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M5M5256DFP-70LLI Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 8 page ![]() RENESAS LSIs 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM M5M5256DFP,VP-55LL,-70LL,-70LLI, -55XL,-70XL 6 Write cycle ( /S control mode) tsu (S) trec (W) th (D) tCW (Note 5) (Note 3) (Note 3) tsu (A) (Note 4) tsu (D) DATA IN STABLE DQ1~8 /S /W A0~14 Note 3 : Hatching indicates the state is "don't care". 5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state. 6 : Don't apply inv erted phase signal externally when DQ pin is output mode. 4 : Writing is executed in ov erlap of /S and /W low. 7 : ten, tdis are periodically sampled and are not 100% tested. (4) MEASUREMENT CONDITIONS Input pulse level .............. VIH=2.4V,VIL=0.6V Input rise and fall time ..... 5ns Reference level ................ VOH=VOL=1.5V Output load ...................... Fig.1 CL=50pF (-55LL,-55XL ) CL=100pF (-70LL,-70LLI,-70XL ) CL=5pF (for ten,tdis) T ransition is measured ±500mV from steady state voltage. (for ten,tdis) Vcc DQ CL Fig.1 Output load 1.8k Ω 990 Ω (Including scope and JIG) |
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