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DS1087L Datasheet(PDF) 5 Page - Dallas Semiconductor |
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DS1087L Datasheet(HTML) 5 Page - Dallas Semiconductor |
5 / 12 page 3.3V Spread-Spectrum EconOscillator _____________________________________________________________________ 5 Note 1: All voltages are referenced to ground. Note 2: This is the absolute accuracy of the master oscillator frequency at the default settings. Note 3: This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at TA = +25°C. Note 4: This is the percentage frequency change from the +25°C frequency due to temperature at VCC = 3.3V. Note 5: The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency. Note 6: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize. tstab is equivalent to approximately 512 master clock cycles and depends on the programmed master oscillator frequency. Note 7: Output voltage swings may be impaired at high frequencies combined with high output loading. Note 8: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least tR MAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. Note 9: After this period, the first clock pulse is generated. Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH MIN of the SCL sig- nal) to bridge the undefined region of the falling edge of SCL. Note 11: The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 13: Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr +125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr max VCC biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, and 168hr 121°C/2 ATM Steam/Unbiased Autoclave. Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) ACTIVE SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( °C) 80 70 60 50 40 30 20 10 0 -10 -20 -30 5.5 6.0 6.5 7.0 7.5 5.0 -40 90 VCC = 3.3V FREQUENCY = 66.6MHz OE = PDN = VCC 15pF LOAD 8.2pF LOAD 4.7pF LOAD UNLOADED VOLTAGE (V) 3.5 3.4 2.8 2.9 3.0 3.2 3.1 3.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0 2.7 3.6 ACTIVE SUPPLY CURRENT vs. VOLTAGE FREQUENCY = 66.6MHz OUTPUT UNLOADED OE = PDN = VCC SUPPLY CURRENT vs. PRESCALER PRESCALER (DECIMAL) 100 10 11000 1 2 3 4 5 6 7 0 OUTPUT UNLOADED 3.6V 3.3V 2.7V |
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