3.3V Spread-Spectrum EconOscillator

8

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Detailed Description

Output Frequency

The internal master oscillator can generate a square

wave with a frequency range of 33.3MHz to 66.6MHz.

The master oscillator frequency and output frequency

are factory programmed, although the user can use the

programmable divider to divide the master oscillator

Output Control and Power-Down

Two user control signals control the output. The output-

enable pin, OE, gates the clock output buffer and the

PDN pin disables the master oscillator and turns off the

output for power-sensitive applications (note: the

power-down command must persist for at least two out-

put frequency cycles plus 10

µs for deglitching purpos-

es). On power-up, the output is disabled until power is

stable and the master oscillator has generated 512

clock cycles.

Both controls feature a synchronous enable, which

ensures there are no output glitches when the output is

enabled. The synchronous enable also ensures a con-

stant time interval (for a given frequency setting) from

an enable signal to the first output transition.

Spread Spectrum

The DS1087L can reduce radiated emission peaks. The

output frequency can be dithered 2% or 4% below the

programmed frequency. Although the output frequency

changes when the dither is enabled, the duty cycle

does not change.

The dither is controlled by the J0 bit in the PRESCALER

register and enabled with the SPRD pin. The maximum

spectral attenuation occurs when the prescaler is set to

1. The spectral attenuation is reduced by 2.7dB for

every factor of 2 that is used in the prescaler. This hap-

pens because the prescaler’s divider function tends to

average the dither in creating the lower frequency.

However, the most stringent spectral emission limits are

imposed on the higher frequencies where the prescaler

is set to a low divider ratio.

A triangle-wave generator injects an offset element into

the master oscillator to dither its output. The dither rate

(see Equation 1) is based on the master oscillator fre-

versus dither rate.

Register Summary

The DS1087L registers are used to change the dither

amount, output frequency, and slave address. A sum-

grammed into EEPROM, the settings only need to be

reprogrammed if it is desired to reconfigure the device.

PRESCALER Register

Bit 5:

Output Low or High-Z. The LO/

HIZ bit

controls the output. During power-down,

while the output is deactivated, if the

LO/

HIZ bit is set to 0, the output is high-Z.

If the LO/

HIZ bit is set to 1, the output is

driven low.

Bit 4:

Dither Control. The J0 bit controls the

dither applied to the output. When J0 is

high, 2% peak dither is selected. When

J0 is low, 4% peak dither is selected.

Dither Rate

f

=

0

4096

REGISTER

ADDR

BINARY

FACTORY DEFAULT

ACCESS

PRESCALER

02h

LO/

HIZ

J0

P3

P2

P1

P0

110- - - - - b

R/W

ADDR

0Dh

WC

A2

A1

A0

11110000b

R/W

WRITE EE

3Fh

No Data

—

—

Figure 2. Output Frequency vs. Dither Rate

OUTPUT FREQUENCY

DITHER RATE

0

(1)